This invention relates to an improved method for statically timing circuits comprised of devices fabricated in silicon on insulator (SOI), and more particularly to a method that takes into account the topology of the circuit in which the device is a part. The improved method includes the determination of body voltage ranges of the SOI device, the generation of IV transient models for the device based on low end and high end body voltages, and classifying the devices based on output pull-up and cross over current in order to select IV characteristics of the devices as inputs for estimating path delays through a series of gates composed of SOI devices.
Trademarks: S/390 and IBM are registered trademarks of International Business Machines Corporation, Armonk, N.Y., U.S.A. and Lotus is a registered trademark of its subsidiary Lotus Development Corporation, an independent subsidiary of International Business Machines Corporation, Armonk, N.Y. Other names may be registered trademarks or product names of International Business Machines Corporation or other companies.
Semiconductor FET devices fabricated with bulk silicon CMOS technologies have a single, stable threshold and IV characteristic (i.e. drain current versus gate voltage and drain current versus drain voltage) because the body of such a device is tied to the substrate. Prior art computer programs for statically timing circuits comprised of FET devices fabricated in bulk silicon CMOS use, as inputs, this single, stable IV characteristic in determining the switching speed of the device. In partially-depleted SOI technologies the body is left floating and thus the body potential or voltage varies as the terminals of the device switch and as the body is charged and discharged.
As will be appreciated by those skilled in the art, partially-depleted silicon-on-insulator devices offer significant speed advantages over bulk devices. Maximum device performance is obtained when the body of a device is allowed to float. In a floating-body configuration, the body voltage is determined by the previous switching history of the device.
As the device terminals (gate, drain, and source) switch they capacitively couple to the body and cause its potential to move in the same direction as the terminal. The body potential is increased by the impact ionization as current flows between the drain and source of a device, and the body potential is decreased by various junction leakage mechanisms. The changing body potential modifies both the threshold voltage of the device and the device IV characteristics. It is difficult to establish the body potentials of the devices in a general circuit since the potentials are constantly changing due to the above effects and the switching histories of the devices are not known.
Path delay estimation is based on static timing analysis and is an important process by which one:
identifies any circuit races/hazards which could cause a chip to malfunction.
verifies the operational speed of a chip.
identifies the paths which limit the operational speed.
Race identification and operational speed verification are generally called early and late mode timing, respectively. The delay through an SOI gate (gate built from SOI devices) is thus difficult to estimate as it depends upon the so-called xe2x80x9cstrengthxe2x80x9d of the individual devices.
In one aspect, the present invention provides for a method for generating multiple model abstractions of an SOI device. In an exemplary embodiment, the method includes initializing a source, a drain and a gate terminal of the SOI device to one of a ground potential and a Vdd potential. A body terminal of the SOI device is initialized to one of a predetermined minimum and a predetermined maximum value of a predetermined voltage range of the body of the SOI device, and the drain current is measured during the application of various drain and gate terminal voltages to the SOI device.
In another aspect, a method for generating a cold model abstraction of an SOI NFET device includes initializing a source, a drain and a gate terminal of the SOI NFET device to ground potential. A body terminal of the SOI NFET device is initialized to a predetermined minimum value of a predetermined voltage range of the body of the SOI NFET device, and the drain current is measured during the application of various drain and gate terminal voltages to the SOI NFET device.
In another aspect, a method for generating a hot model abstraction of an SOI NFET device includes initializing a source, a drain and a gate terminal of the SOI NFET to ground potential. A body terminal of the SOI NFET device is initialized to a predetermined maximum value of a predetermined voltage range of the body of the SOI NFET device, and the drain current is measured during the application of various drain and gate terminal voltages to the SOI NFET device.
In still another aspect, a method for generating a cold model abstraction of an SOI PFET device includes initializing a source, a drain and a gate terminal of the SOI PFET device to a Vdd potential. A body terminal of the SOI PFET device is initialized to a predetermined maximum value of a predetermined voltage range of the body of the SOI PFET device, and to drain current is measured during the application of various drain and gate terminal voltages to the SOI PFET device.
In still another aspect, a method for generating a cold model abstraction of an SOI PFET device includes initializing a source, a drain and a gate terminal of the SOI PFET device to a Vdd potential. A body terminal of the SOI PFET device is initialized to a predetermined maximum value of a predetermined voltage range of the body of the SOI PFET device, and the drain current is measured during the application of various drain and gate terminal voltages to the SOI PFET device.